In recent years, in order to increase the degree of integration of large-scale integrated circuit devices (hereinafter referred to as LSIs) using a semiconductor, the size of a circuit pattern has been further reduced. As a result, great importance is placed on refinement of a line feature forming a circuit and a reduction in the size of a contact hole, etc., for connecting multilayered interconnects through insulating layers, and a finer feature than the finest feature which can be formed by being exposed to light using lithography has needed to be formed.
With such a reduction in the circuit pattern size, it has been more difficult to allow the finished dimensions of some layout features forming certain shapes to coincide with the intended design dimensions thereof. This is due to the influence of, e.g., an optical proximity effect in a lithography process step out of essential process steps of an LSI fabrication process, and a microloading effect in an etching process step out of them.
To address this problem, methods are introduced in which the feature dimensions and shape of an exposure mask are corrected by performing accurate simulation to provide intended finished dimensions. Examples of the methods include optical proximity correction (OPC). However, it is difficult to provide an accuracy high enough to correct large-scale data, and an enormous amount of calculation time for the correction is also required.
Therefore, a method has been proposed in which dummy features are placed to reduce layout variations causing the above-described effects, i.e., to achieve uniform feature densities, etc. The dummy features do not substantially function as portions of a circuit, and are provided, e.g., in order to increase the accuracy of finished features and reduce poorly patterned features.
A portion of a circuit pattern which needs to have finished dimensions with the highest accuracy is related to the structure of a transistor. This will be described with reference to FIG. 13 illustrating a layout of a metal oxide semiconductor (MOS) transistor. As illustrated in FIG. 13, a line feature 10 representing a gate layer includes a line portion overlapping with an active layer shape 11 representing an active layer. The overlapping line portion forms a gate portion 13 of the transistor. Portions of the active layer shape 11 between which the gate portion 13 is interposed form source/drain features 14 of the transistor. The line width of the gate portion 13 interposed between the source/drain features 14 is referred to as a gate length 13A, and this value has a significant influence on operation of the transistor.
The gate portion 13 includes line end portions protruding beyond the active layer shape 11. The line end portions are referred to as gate protruding portions 15, and unless the gate protruding portions 15 are each of adequate size, a leakage current is generated between the source and drain of the transistor, thereby causing a serious problem in circuit operation. Furthermore, in recent years, it has been recognized that a protrusion length 15A denoting the length of each of the gate protruding portions 15 which were previously considered to merely need to be of adequate size also has an influence on circuit operation. Thus, the dimensional accuracy of the protruding portion 15 has also become significant.
Next, a method for improving the accuracy of the line width as described in Japanese Patent Publication No. H09-311432 will be described with reference to FIGS. 14A and 14B. FIG. 14A illustrates a situation where real features 21 and dummy features 22 are placed in the above-described method, and FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb′ in FIG. 14A. As illustrated in FIGS. 14A and 14B, the real features 21 are formed on a semiconductor substrate 20, and the dummy features 22 are formed on an empty region of the semiconductor substrate 20 on which the real features 21 are not formed. The dummy features 22 each have a width substantially equal to that of each of the real features 21, and are spaced at intervals equal to the interval between each adjacent pair of the real features 21. Such provision of the dummy features 22 allows the feature density to be substantially uniform, thereby improving the accuracy of the line width of each of the line features.
Next, a method for improving the accuracy of the width of a line end portion as described in Japanese Patent Publication No. H11-095406 will be described with reference to FIGS. 15A and 15B. In these figures, real features 30 which are interconnect features, and dot-shaped dummy features 31 located in the vicinities of line end portions of the real features 30 are illustrated. The dot-shaped dummy features 31 can be spaced apart from the real features 30 by a distance substantially equal to the shortest distance between the adjacent interconnect features, and thus, the feature density differences among the vicinities of the line end portions are reduced, thereby reducing variations in finished dimensions.